1. Field of the Invention
The present invention relates to a method, system, and program for processing transaction requests during a pendency of a delayed read request.
2. Description of the Related Art
The Peripheral Component Interconnect (PCI) bus architecture provides a low latency path through which devices implementing the PCI architecture can communicate. Details of the PCI bus architecture are described in the publication “PCI Local Bus Specification,” Revisions 2.2 (December 1998), published by the PCI Special Interest Group, which publication is incorporated herein by reference in its entirety. Each PCI device, also referred to as a bus master or target, that communicates on the PCI bus includes a configuration space including information used to address the device on the PCI bus.
The PCI specification provides for delayed transaction processing. In delayed transactions, the master submitting a read request is disconnected from the bus while the target device accesses and buffers the requested data. The master initiating the read would continually retry the read until the requested data is gathered in the buffer. When the master retries the read request after the target has gathered the requested data, the data will then be returned to the master. In this way, the bus is not held in wait states while the read data is gathered and other devices can access the PCI bus. This is especially important for read requests directed toward slower target devices where the read operation can take longer to complete. In such cases, the delayed read request will avoid the lengthy read operation from occupying the bus and preventing other devices access during the lengthy read.
When multiple masters are connected to the PCI bus, other master requests may take control of the PCI bus for extended periods and prevent the master that was disconnected for the delayed read transaction from accessing the requested read data from the buffer for the extended period. For instance, if after a master disconnects as part of a delayed read transaction, another master can submit a posted write. The master that submitted the read may not reconnect and retrieve the data until the intervening write request has completed. Such delays due to an intervening write can add significant delays to the read request, especially for lengthier writes. A posted write is a write where upon transferring the data to an intermediate agent, such as the target in a PCI device or bridge, the transaction completes at the originating agent before it completes at the intended destination, e.g., the data is written to the target device. This allows the originating agent to proceed with the next transaction while the requested transaction is working its way to the ultimate destination.
In the prior art, the read master can only reconnect after the master write completes the transfer of data across the bus or after a latency timer expires, which effectively places an upper limit on any master's access. After the posted write has completed on the PCI bus or the latency timer has expired, the write master is disconnected and the read master can reconnect to access the buffered data. Such delays to the read request can be extensive if the write request is lengthy. Moreover, the latency timer is often set to a value much longer than the time required for the target to fetch the requested read data, thus causing latency from the time the data is available to when the latency timer expires.
One goal of PCI bus designers is to minimize read latency delays. Read latency is a result of both the delays that occur when accessing the data from the target device and any delays resulting from other masters gaining control of the PCI bus and preventing the delay read master from reconnecting, which occurs in the case of a posted write. If the system performance is particularly sensitive to read latency delays, then the frequent occurrence of such delays may degrade system performance. For these reasons, there is a need in the art to reduce read latency delays that occur when intervening requests, such as posted writes, prevent the master initiating the delayed read transaction from reconnecting to the bus to access the buffered read request data.